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ir3084u page 1 of 47 june 1, 2009 xphase tm vr10, vr11 & opteron/athlon64 control ic description the ir3084u control ic combined with an ir xphase tm phase ic provides a full featured and flexible way to implement a complete vr10, vr11, opteron, or athlon64 power solution. the control ic provides overall system control and interfaces with any number of phase ics which each drive and monitor a single phase of a multiphase converter. t he x phase tm architecture results in a power supply that is smaller, less expensive, and easier to desi gn while providing higher efficiency than conventio nal approaches. the ir3084u is based on the ir3084 vr10 control ic, but incorporates the following modifications; supports vr11 7-bit vid, vr10 7-bit extended vid, and opteron/athlon64 5-bit vid codes supports both vr11 and legacy opteron/athlon64 sta rt-up sequences vid select pin sets the dac to vr10, vr11, or opte ron/athlon64 intl_md output pin indicates which dac is selected C intel or amd vosens? float detection protects the cpu in the ev ent that the vosens? trace is broken enable input thresholds set by vid select pin to e ither vr10, vr11 or opteron/athlon64 vid input thresholds set by vid select pin to eith er 0.6v (vr10/vr11) or 1.24v (amd) no-load setpoint current changes polarity based on vid select to accommodate vr10, vr11 (negative offset from dac) or opteron/athlon64 (pos itive offset from dac). features 1 to x phase operation with matching phase ic 7-bit vr 10/11 compatible vid with 0.5% overall sy stem set point accuracy 5-bit opteron/athlon64 compatible vid with 1% over all system set point accuracy programmable dynamic vid slew rate +/-300mv differential remote sense programmable vid offset voltage at the error ampli fiers non-inverting input allows zero offset programmable 150khz to 1mhz oscillator programmable vid offset and load line output imped ance programmable hiccup over-current protection with d elay to prevent false triggering simplified vr ready output provides indication of proper operation and avoids false triggering operates from 12v input with 9.9v under-voltage lo ckout 6.8v/6ma bias regulator provides system reference voltage phase ic gate driver bias regulator / vrhot compar ator reduced over-current detect delay eliminates and e xternal resistor in typical applications small thermally enhanced 28l mlpq package downloaded from: http:///
ir3084u page 2 of 47 june 1, 2009 typical application circuit rdrp1 750 q6 rosc 30.1k vid0 outen rocset 12.7k vid2 vid1 rvsetpt 124 vid4 vid3 css/del 0.1uf vid6 vid5 rfb1 162 vid_sel c89 100pf rcp 2.49k rdrp 750 vss_sense cfb 12nf ccp1 100pf +5.0v rvgdrv 97.6k vr_rdy vreg_12v_filtered ea ccp 56nf r137 2k ishare r117 1.21k rvsetpt1 124 rmp cvgdrv 10nf cvdac 33nf rvdac 3.5 vdac c1009 1nf r30 10 c130 0.1uf c134 0.1uf vid5 4 vid0 9 vid1 8 vid2 7 vid3 6 vid4 5 rmpout 19 lgnd 22 vdac 12 ss/del 26 enable 28 vosns-- 10 fb 17 regdrv 24 rosc 11 regset 25 vdrp 16 iin 15 eaout 18 vcc 21 vid6 3 intl_md 2 vrrdy 27 vsetpt 14 vidsel 1 vbias 20 regfb 23 ocset 13 u5 ir3084umtr rfb 348 rt2 4.7k, b=4450 vcc_sense vreg_12v_filtered c204 0.1uf q4 cjd200 r1331 1 c135 1uf vgdrive vbias q5 downloaded from: http:///
ir3084u page 3 of 47 june 1, 2009 ordering inforamation device order quantity ir3084umtrpbf 3000 tape and reel IR3084UMPBF 100 piece strip absolute maximum ratings operating junction temperature..0 to 150 o c storage temperature range.?65 o c to 150 o c esd ratinghbm class 1b jedec standar d moisture sensitivity leveljedec level 2 @ 260 o c pin # pin name v max v min i source i sink 1 vidsel 20v -0.3v 1ma 1ma 2 intl_md 20v -0.3v 1ma 1ma 3-9 vid6?vid0 20v -0.3v 1ma 1ma 10 vosns- 0.5v -0.5v 10ma 10ma 11 rosc 20v -0.5v 1ma 1ma 12 vdac 20v -0.3v 1ma 1ma 13 ocset 20v -0.3v 1ma 1ma 14 vsetpt 20v -0.3v 1ma 1ma 15 iin 20v -0.3v 1ma 1ma 16 vdrp 20v -0.3v 5ma 5ma 17 fb 20v -0.3v 1ma 1ma 18 eaout 10v -0.3v 20ma 20ma 19 rmpout 20v -0.3v 5ma 5ma 20 vbias 20v -0.3v 50ma 10ma 21 vcc 20v -0.3v 1ma 50ma 22 lgnd n/a n/a 50ma 1ma 23 regfb 20v -0.3v 1ma 1ma 24 regdrv 20v -0.3v 10ma 50ma 25 regset 20v -0.3v 1ma 1ma 26 ss/del 20v -0.3v 1ma 1ma 27 vrrdy 20v -0.3v 1ma 20ma 28 enable 20v -0.3v 1ma 1ma downloaded from: http:///
ir3084u page 4 of 47 june 1, 2009 electrical specifications unless otherwise specified, these specifications ap ply over: 9.5v v cc 16v, ?0.3v vosns- 0.3v, 0 o c t j 100 o c, rosc = 24k , css/del = 0.1 f 10% parameter test condition min typ max unit vdac reference vid 1v, 10k rosc 100k , 25 o c t j 100 o c ?0.5 0.5 % vr10/vr11 system set-point accuracy (deviation from tables 1 & 2 per test circuit in figure 1 which emulates in-vr operation) 0.8v vid < 1v, 10k rosc 100k , 25 o c t j 100 o c ?5 +5 mv opteron/athlon64 system set- point accuracy 25 o c t j 100 o c ?1 1 % source current includes ocset and vsetpt currents 104 113 122 a sink current includes ocset and vsetpt currents 92 100 108 a vr10/vr11 vidx input threshold 500 600 700 mv opteron/athlon64 vidx input threshold 1.04 1.24 1.44 v vidx input bias current 0v < vidx < vcc ?5 0 5 a vidx 11111x blanking delay measure time till vrrdy drives low 0.5 1.3 2.1 s vidsel pull up voltage vidsel floating 1.95 2.4 2.8 5 v vidsel pull up resistor 2.25 4.5 9 k vidsel vr10/opteron threshold vidsel low 0.5 0.6 0.7 v vidsel opteron voltage 6.49k from vidsel to gnd 0.9 1.3 1.7 v vidsel opteron/vr11 threshold 1.8 1.95 2.1 v error amplifier input offset voltage measure v(fb) C v(vsetpt) per test circuit in figure 1. applies to all vid codes. note 2. ?5 0.0 5 mv fb bias current ?1 ?0.1 0.5 a vsetpt bias current vr10/vr11 mode 48.5 51 53.5 a vsetpt bias current opteron/athlon64 mode ?54 ?47 ? 39 a dc gain note 1 90 100 110 db gain bandwidth product note 1 6 10 mhz corner frequency 45 deg phase shift, note 1 200 40 0 hz slew rate note 1 1.4 3.2 5 v/ s source current ?1.2 ?0.7 ?0.35 ma sink current 0.5 1.1 1.7 ma max voltage vbiasCveaout (referenced to vbias) 150 350 600 mv min voltage normal operation or fault mode 30 125 2 00 mv downloaded from: http:///
ir3084u page 5 of 47 june 1, 2009 parameter test condition min typ max unit current sense input iin bias current v(ss/del) > 0.85v, v(eaout) > 0.5v ?2.0 ?0.2 1.0 a iin preconditioning pull-down resistance v(ss/del) < 0.35v 5.6 12.5 19.4 k iin preconditioning reset threshold v(eaout) 0.20 0.35 0.50 v iin preconditioning set threshold v(ss/del) 0.35 0.60 0.85 v vdrp buffer amplifier input offset voltage v(vdrp) C v(iin), 0.5v < v(iin ) < 5v ?10 ?2 6 mv source current 0.5v < v(iin) < 5v ?9.0 ?6.8 ?4.0 ma sink current 0.5v < v(iin) < 5v 0.2 0.85 4.1 ma bandwidth (-3db) note 1 1 6 mhz slew rate note 1 5 10 v/ s vbias regulator output voltage ?5ma < i(vbias) < 0ma 6.6 6.9 7.2 v current limit ?35 ?20 ?6 ma over-current comparator input offset voltage 1v < v(ocset) < 5v ?10 0 10 mv ocset bias current ?53.5 ?51 ?48.5 a soft start and delay start delay (td1) rdrp = 1.2 1.8 2.6 ms soft start time (td2) rdrp = , time to reach 1.1v 0.8 1.8 2.8 ms vid sample delay (td3) vr10/vr11 mode only 0.2 1.0 2.5 ms dvid slew time & vrrdy delay (td4+td5) vr10/vr11 mode only 0.5 1.3 2.2 ms powergood delay opteron/athlon64 mode. measured from vcore=1.1v to when vrrdy transitions hi. 0.7 2.3 4.7 ms oc delay time 150 250 350 us ss/del to fb input offset voltage with fb = 0v, adjust v(ss/del) until eaout drives high 0.85 1.3 1.5 v ss/del charge current 40 70 100 a ss/del discharge current 4 6.5 9 a charge/discharge current ratio 9.5 11.2 12.5 a/ a oc discharge current note 1 20 40 60 a charge voltage 3.6 3.85 4.1 v oc/vrrdy delay comparator threshold relative to charge voltage, ss/del rising 80 mv oc/vrrdy delay comparator threshold relative to charge voltage, ss/del falling 100 mv delay comparator hysteresis note 1 20 mv vid sample delay comparator threshold vr10/vr11 mode only 3.10 v ss/del discharge comparator threshold 215 mv downloaded from: http:///
ir3084u page 6 of 47 june 1, 2009 parameter test condition min typ max unit vrrdy output output voltage i(vrrdy) = 4ma 150 300 mv leakage current v(vrrdy) = 5.5v 0 10 a enable input vr10/11 threshold voltage enable rising 800 850 90 0 mv vr10/11 threshold voltage enable falling 700 750 8 00 mv vr10/11 threshold hysteresis 70 100 130 mv opteron/athlon64 threshold voltage enable rising 1.11 1.23 1.35 v opteron/athlon64 threshold voltage enable falling 1.06 1.17 1.29 v opteron/athlon64 threshold hysteresis 35 60 85 mv input resistance 50 100 200 k blanking time noise pulse < 250ns will not register an enable state change. note 1 75 250 400 ns oscillator switching frequency rosc = 24k 450 500 550 khz peak voltage (4.8v typical, measured as % of vbias) 70 71 74 % valley voltage (0.9v typical, measured as % of vbias) 10 13 15 % intl_md output source current v(intl_md)=2v, vr10 or vr11 mode 100 200 300 a sink current v(intl_md)=2v, opteron mode 250 750 15 00 a max voltage pin floating, v(vbias)?v(intl_md) 50 17 0 350 mv min voltage pin floating, lgnd referenced 400 900 mv vosns? float detect detect voltage v(vosns?) with respect to v(lgnd), verify v(vrrdy) and v(eaout) are low. 1.2 2 2.6 v detect delay v(vosns-) 0v to 2.6v step, measure time when v(vrrdy) falls. note 1 200 350 600 ns driver bias regulator regset bias current 1.5v < v(regset) < vcc C 1.5v ? 112 ?99 ?85 a input offset voltage 1.5v < v(regset) < vcc C 1.5v, 100 a < i(regdrv) < 10ma ?12 0 12 mv short circuit current v(regdrv) = 0v, 1.5v < v(regset) < vcc C 1.5v, note 1 10 20 50 ma dropout voltage i(regdrv) = 10ma, note 1 0.4 0.87 1 .33 v downloaded from: http:///
ir3084u page 7 of 47 june 1, 2009 parameter test condition min typ max unit vcc under-voltage lockout start threshold 9.3 9.9 10.3 v stop threshold 8.5 9.1 9.5 v hysteresis start C stop 550 800 1000 mv general vcc supply current 9 14 18 ma vosns? current ?0.3v < vosns? < 0.3v, all vid codes ?1.45 ?1.1 ?0.75 ma note 1: guaranteed by design, but not tested in production note 2: vdac output is trimmed to compensate for error amp input offsets errors 200 ohm +- + isink intel: +ioffset amd: --ioffset "fast" vdac - isource error amp vdac buffer amp irosc irosc iocset rosc buffer amp current source generator + - 1.2v +- + - eaout vsetpt fb vdac ocset rosc vosns- ir3084u rosc rvdac cvdac 200 ohm system set point voltage figure 1 C system set point test circuit downloaded from: http:///
ir3084u page 8 of 47 june 1, 2009 pin descriptions pin# pin symbol description 1 vidsel selects the dac table and the type of soft start. there are 3 possible modes of operation: (1) gnd selects vr10 dac and vr11 type s tartup, (2) float (2.4v) selects vr11 dac and vr11 type startup, (3) 6.49k t o gnd (1.3v) selects opteron/athlon64 dac and legacy type startup. addi tional details are provided in the theory of operation section. 2 intl_md output that indicates if the controller is in intel mode or amd mode. this pin will be low when in amd mode and high when in intel mode. 3-9 vid6?vid0 inputs to the d to a converter. must be connected to an external pull up resistor. 10 vosns? negative remote sense input. connect to ground at t he load. 11 rosc connect a resistor from this pin to vosns? to progr am the oscillators frequency, ocset, vsetpt, regset, and vdac bias currents. 12 vdac regulated output voltage programmed by the vid inpu ts. connect an external rc network to from this pin to vosns? to program the d ynamic vid slew rate and provide compensation for the internal buffer amplif ier. 13 ocset programs the hiccup over-current threshold through an external resistor tied to vdac and an internal current source. over-current p rotection can be disabled by connecting a resistor from this pin to vdac to prog ram the threshold higher than the possible signal into the iin pin from the phase ics but no greater than 5v (do not float this pin as improper operation will occur). 14 vsetpt error amp non-inverting input. the converters outp ut voltage can be decreased (intel) or increased (amd) from the vdac voltage wi th an external resistor connected between vdac and an internal current sour ce. current sensing and pwm operation are referenced to this pin. 15 iin current sense input from the phase ic(s). prior to startup, when ss/del<0.6v, this pin is pulled low by a 12.5k resistor to disable cu rrent balancing in the phase ics. when ss/del>0.6v and eaout>0.35v, this pin is relea sed and current balancing is enabled. if avp or over-current protection is n ot required, connect this pin to vdac. to ensure proper do not float this pin. 16 vdrp buffered iin signal. connect an external resistor f rom this pin to the fb pin to set the converters output impedance. 17 fb inverting input to the error amplifier. 18 eaout output of the error amplifier. when low, provides uvl function to the phase ics. 19 rmpout oscillator output voltage. used by the phase ics to program phase delay. 20 vbias 6.9v/6ma regulated output used as a system referenc e voltage for internal circuitry and for phase timing at the phase ics. 21 vcc power input for the internal circuitry. 22 lgnd local ground for internal circuitry and ic substrat e connection 23 regfb inverting input of the bias regulator error amp. co nnect this pin to the collector of the phase ic gate driver bias transistor. 24 regdrv output of the bias regulator error amp. 25 regset non-inverting input of the bias regulator error amp . the output voltage of the phase ic gate driver bias regulator is set by an in ternal current source supplying an external resistor connected from this pin to gro und. 26 ss/del controls converter start-up and over-current timing . connect an external capacitor from this pin to lgnd to program the soft start and delay times. 27 vrrdy open collector output that drives low during start- up and when any external fault occurs. connect external pull-up resistor. 28 enable enable input. a logic low applied to this pin puts the ic into fault mode. this pin has a 100k pull-down resistor to gnd. downloaded from: http:///
ir3084u page 9 of 47 june 1, 2009 system theory of operation xphase tm architecture the xphase tm architecture is designed for multiphase interleave d buck converters which are used in applications requiring small size, design flexibili ty, low voltage, high current and fast transient re sponse. the architecture can be used in any multiphase converte r ranging from 1 to 16 or more phases where flexibi lity facilitates the design trade-off of multiphase conv erters. the scalable architecture can be applied to other applications which require high current or multiple output voltages. as shown in figure 2, the xphase tm architecture consists of a control ic and a scalab le array of phase converters each using a single phase ic. the contro l ic communicates with the phase ics through a 5-wi re analog bus, i.e. bias voltage, phase timing, averag e current, error amplifier output, and vid voltage. the control ic incorporates all the system functions, i.e. vid, pwm ramp oscillator, error amplifier, bias voltage , and fault protections etc. the phase ic implements the functi ons required by the converter of each phase, i.e. t he gate drivers, pwm comparator and latch, over-voltage pro tection, and current sensing and sharing. there is no unused or redundant silicon with the xphase tm architecture compared to others such as a 4 phase controller that can be configured for 2, 3, or 4 ph ase operation. pcb layout is easier since the 5 wi re bus eliminates the need for point-to-point wiring betwe en the control ic and each phase. the critical gate drive and current sense connections are short and local to th e phase ics. this improves the pcb layout by loweri ng the parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal. vr fan vid3 additional phases input/output control bus cout >> vid voltage vid0 vid1 vid2 vout sense+ vr hot vr ready ir3084 control ic >> pwm control >> phase timing >> bias voltage << current sense rcs ccs cin rcs ccs vid6 vid5 vidsel vid4 vout- vout sense- 12v vout+ enable ir3086 phase ic phase fault ir3086 phase ic current share current share phase fault phase fault figure 2 C system block diagram downloaded from: http:///
ir3084u page 10 of 47 june 1, 2009 pwm control method the pwm block diagram of the xphase tm architecture is shown in figure 3. feed-forward vo ltage mode control with trailing edge modulation is used. a high-gain wide-bandwidth voltage type error amplifier in the control ic is used for the voltage control loop. an external rc c ircuit connected to the input voltage and ground is used to program the slope of the pwm ramp and to provide th e feed-forward control at each phase. the pwm ramp slope will change with the input voltage and automa tically compensate for changes in the input voltage . the input voltage can change due to variations in the silver box output voltage or due to drops in the pcb relat ed to changes in load current. vsetpt rvsetpt rcs pwm comparator gnd vout rvfb system reference voltage vbias +- vbias regulator vdac biasin pwmrmp + - + - clock pulse generator dacin ramp discharge clamp enable + - vosns+ rampin+ vosns- +- rampin- ishare vosns- rdrp vdrp + - iin scomp o% duty cycle comparator vdrp amp vdac ioffset + - + - gateh + - csin+ gatel eain csin- vpeak 50% duty cycle ramp generator vvalley rmpout + - rramp1 rramp2 current sense amp reset dominant pwm latch s share adjust error amp x34 r error amp ramp slope adjust irosc eaout x 0.91 fb control ic cout 20mv +- 10k + - + - + - + - +- 10k + - + - rramp1 ccs rcs rramp2 biasin rampin- eain ishare pwmrmp scomp rampin+ csin+ gateh dacin csin- gatel vin phase ic phase ic pwm latch current sense amp share adjust error amp x34 reset dominant sr clock pulse generator 20mv pwm comparator enable ramp slope adjust ramp discharge clamp system reference voltage o% duty cycle comparator x 0.91 ccs cscomp cpwmrmp rpwmrmp cscomp cpwmrmp rpwmrmp figure 3 C ir3084u pwm block diagram frequency and phase timing control the oscillator is located in the control ic and its frequency is programmable from 150khz to 1mhz by a n external resistor. the output of the oscillator is a 50% dut y cycle triangle waveform with peak and valley volt ages of approximately 5v and 1v. this signal is used to pro gram both the switching frequency and phase timing of the phase ics. the phase ic is programmed by resistor d ivider rramp1 and rramp2 connected between the vbias reference voltage and the phase ic lgnd pin. a comparator in the phase ics detects the crossing of the oscillator waveform with the voltage generated by t he resistor divider and triggers a clock pulse that starts the pwm cycle. the peak and valley voltages track the v bias voltage reducing potential phase ic timing err ors. figure 4 shows the phase timing for an 8 phase conv erter. note that both slopes of the triangle wavefo rm can be used for synchronization by swapping the ramp + and C pins. downloaded from: http:///
ir3084u page 11 of 47 june 1, 2009 ramp (from control ic) clk1 vvalley (1.00v) phase ic clock pulses vphase1&8 (1.5v) vphase3&6 (3.5v) vphase2&7 (2.5v) vphase4&5 (4.5v) vpeak (5.0v) clk2 50% ramp duty cycle clk3 clk4 clk5 clk6 clk7 clk8 slope = 80mv / % dc slope = 1.6mv / ns @ 200khz slope = 8.0mv / ns @ 1mhz figure 4 C 8 phase oscillator waveforms pwm operation the pwm comparator is located in the phase ic. upon receiving a clock pulse, the pwm latch is set, the pwmrmp voltage begins to increase, the low side dri ver is turned off, and the high side driver is then turned on. when the pwmrmp voltage exceeds the error amps out put voltage the pwm latch is reset. this turns off the high side driver, turns on the low side driver, and activates the ramp discharge clamp. the clamp quic kly discharges the pwmrmp capacitor to the vdac voltage of the control ic until the next clock pulse. the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nano seconds in response to a load step decrease. phases can overla p and go to 100% duty cycle in response to a load s tep increase with turn-on gated by the clock pulses. an error amp output voltage greater than the common m ode input range of the pwm comparator results in 100% d uty cycle regardless of the voltage of the pwm ramp . this arrangement guarantees the error amp is always in c ontrol and can demand 0 to 100% duty cycle as requi red. it also favors response to a load step decrease which is appropriate given the low output to input voltag e ratio of most systems. the inductor current will increase mu ch more rapidly than decrease in response to load t ransients. this control method is designed to provide single cycle transient response where the inductor curren t changes in response to load transients within a single swit ching cycle maximizing the effectiveness of the pow er train and minimizing the output capacitor requirements. an additional advantage is that differences in grou nd or input voltage at the phases have no effect on operation s ince the pwm ramps are referenced to vdac. downloaded from: http:///
ir3084u page 12 of 47 june 1, 2009 body braking tm in a conventional synchronous buck converter, the m inimum time required to reduce the current in the i nductor in response to a load step decrease is; t slew = [l x (i max - i min )] / vout the slew rate of the inductor current can be signif icantly increased by turning off the synchronous re ctifier in response to a load step decrease. the switch node v oltage is then forced to decrease until conduction of the synchronous rectifiers body diode occurs. this inc reases the voltage across the inductor from vout to vout + v body diode . the minimum time required to reduce the current in the inductor in response to a load transient decrease is now; t slew = [l x (i max - i min )] / (vout + v body diode ) since the voltage drop in the body diode is often h igher than output voltage, the inductor current sle w rate can be increased by 2x or more. this patent pending techni que is referred to as body braking and is accompl ished through the 0% duty cycle comparator located in t he phase ic. if the error amps output voltage drop s below 91% of the vdac voltage this comparator turns off t he low side gate driver. figure 5 depicts pwm operating waveforms under vari ous conditions phase ic clock pulse eain vdac pwmrmp gateh gatel steady-state operation duty cycle decrease due to vin increase (feed-forward) duty cycle increase due to load increase duty cycle decrease due to load decrease (body braking) or fault (vcc uv, vccvid uv, ocp, vid=11111x) steady-state operation body braking threshold figure 5 C pwm operating waveforms lossless average inductor current sensing inductor current can be sensed by connecting a seri es resistor and a capacitor network in parallel wit h the inductor and measuring the voltage across the capac itor. the equation of the sensing network is, s s l l s s l c c sr sl r s i c sr s v s v + + = + = 1 )( 1 1 )( )( usually the resistor rcs and capacitor ccs are chos en so that the time constant of rcs and ccs equals the time constant of the inductor which is the inductance l over the inductor dcr. if the two time constants ma tch, the voltage across ccs is proportional to the current t hrough l, and the sense circuit can be treated as i f only a sense resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component o f the inductor current. downloaded from: http:///
ir3084u page 13 of 47 june 1, 2009 the advantage of sensing the inductor current versu s high side or low side sensing is that actual outp ut current being delivered to the load is obtained rather than peak or sampled information about the switch curre nts. the output voltage can be positioned to meet a load lin e based on real time information. except for a sens e resistor in series with the inductor, this is the only sense me thod that can support a single cycle transient resp onse. other methods provide no information during either load i ncrease (low side sensing) or load decrease (high s ide sensing). an additional problem associated with peak or valle y current mode control for voltage positioning is t hat they suffer from peak-to-average errors. these errors wi ll show in many ways but one example is the effect of frequency variation. if the frequency of a particul ar unit is 10% low, the peak to peak inductor curre nt will be 10% larger and the output impedance of the converter wi ll drop by about 10%. variations in inductance, cur rent sense amplifier bandwidth, pwm prop delay, any added slop e compensation, input voltage, and output voltage a re all additional sources of peak-to-average errors. current sense amplifier a high speed differential current sense amplifier i s located in the phase ic, as shown in figure 6. it s gain decreases with increasing temperature and is nomina lly 34 at 25oc and 29 at 125oc (-1470 ppm/oc). this reduction of gain tends to compensate the 3850 ppm/ oc increase in inductor dcr. since in most designs the phase ic junction is hotter than the inductor these two effects tend to cancel such that no additional temperature compensation of the load line is required. the current sense amplifier can accept positive dif ferential input up to 100mv and negative up to -20m v before clipping. the output of the current sense amplifier is summed with the dac voltage and sent to the con trol ic and other phases through an on-chip 10k resistor connected to the ishare pin. the ishare p ins of all the phases are tied together and the voltage on the sha re bus represents the average inductor current thro ugh all the inductors and is used by the control ic for voltage positioning and current limit protection. figure 6 C inductor current sensing and current se nse amplifier average current share loop current sharing between phases of the converter is achieved by the average current share loop in each phase ic. the output of the current sense amplifier is co mpared with the share bus less a 20mv offset. if cu rrent in a phase is smaller than the average current, the shar e adjust amplifier of the phase will activate a cur rent source that reduces the slope of its pwm ramp thereby incr easing its duty cycle and output current. the cross over frequency of the current share loop can be programm ed with a capacitor at the scomp pin so that the sh are loop does not interact with the output voltage loop. c o l r l r s c s v o csa co i l v l v c downloaded from: http:///
ir3084u page 14 of 47 june 1, 2009 ir3084u theory of operation block diagram 2.0v no cpu +- + - + - over current bias regulator error amp + - + - +- + - + - discharge comparator iregset disable start latch r s set dominant no cpu latched irosc irosc irosc irosc irosc irosc irosc irosc irosc 3.1v vosns open +- 6.9v + - 1.17v 1.23v vid sample delay comparator +- r vid4 vosns- vid fault latch irosc s set dominant vid1 vid0 vid2 vidsel vid3 vdac + - no_cpu + 1.3v ichg 70ua 50% duty cycle vdrp amp 4.8v vchg 3.85v 850mv oc discharge current 40ua r 1.3us blanking 9.9v fault latch ss/del discharge 6.5ua vid6 vid5 100mv 80mv rosc buffer amp isink oc comparator 0.9v current source generator iocset ramp generator 1.95v 0.6v set dominant digital to analog converter 750mv intel: ioffset amd: -ioffset vid input comparators (1 of 9 shown) "fast" vdac intel: 0.6v amd: 1.24v vcc uvlo comparator ihiccup discharge - vbias regulator 4.5k on isource 100k delay comparator s softstart clamp enable comparator vsetpt off 0.215v error amp 9.1v 1.2v on vdac buffer amp 12.5k intl_md regdrv regfb regset fb eaout + - + +- disable vosns float detect irosc vcc irosc irosc 250ns blanking vbias +- + - + - +- +- + - + - + - +- + - iin +- ocset enable rosc vcc lgnd vdrp ss/del vbias vrrdy rmpout irosc amd intel uvlo + - + - + - intl_md 2.4v intel/amd 1.1v vid = 1.1v boot r s set dominant iin preconditioning latch +- +- 0.6v 0.35v figure 7 C ir3084u block diagram vid control a 7-bit vid voltage compatible with vr10 (see table 1) and vr11 (see table 2) and opteron/athlon64 (se e table 3) is available at the vdac pin. the vidsel p in configures the dac for vr10 if grounded, vr11 if floating, and opteron/athlon64 if connected to gnd via a 6.4k resistor. the vidsel pin is internally p ulled-up to 2.4v through a 4.5kohm resistor. the vid pins requi re an external bias voltage and should not be float ed. the vid input comparators, with 0.6v reference for vr10 /vr11 and 1.24v for opteron/athlon64, monitor the v id pins and control the 7-bit digital-to-analog conver ter (dac) whose output is sent to the vdac buffer a mplifier. the output of the buffer amp is the vdac pin. the vdac voltage is post-package trimmed to compensate for the input offsets of the error amp to provide a 0.5 % system accuracy. the actual vdac voltage does no t represent the system set point and has a wider tole rance. downloaded from: http:///
ir3084u page 15 of 47 june 1, 2009 vid4 vid3 vid2 vid1 vid0 vid5 vid6 voltage vid4 vid3 vid2 vid1 vid0 vid5 vid6 voltage 0 1 0 1 0 1 1 1.60000 1 1 0 1 0 1 1 1.20000 0 1 0 1 0 1 0 1.59375 1 1 0 1 0 1 0 1.19375 0 1 0 1 1 0 1 1.58750 1 1 0 1 1 0 1 1.18750 0 1 0 1 1 0 0 1.58125 1 1 0 1 1 0 0 1.18125 0 1 0 1 1 1 1 1.57500 1 1 0 1 1 1 1 1.17500 0 1 0 1 1 1 0 1.56875 1 1 0 1 1 1 0 1.16875 0 1 1 0 0 0 1 1.56250 1 1 1 0 0 0 1 1.16250 0 1 1 0 0 0 0 1.55625 1 1 1 0 0 0 0 1.15625 0 1 1 0 0 1 1 1.55000 1 1 1 0 0 1 1 1.15000 0 1 1 0 0 1 0 1.54375 1 1 1 0 0 1 0 1.14375 0 1 1 0 1 0 1 1.53750 1 1 1 0 1 0 1 1.13750 0 1 1 0 1 0 0 1.53125 1 1 1 0 1 0 0 1.13125 0 1 1 0 1 1 1 1.52500 1 1 1 0 1 1 1 1.12500 0 1 1 0 1 1 0 1.51875 1 1 1 0 1 1 0 1.11875 0 1 1 1 0 0 1 1.51250 1 1 1 1 0 0 1 1.11250 0 1 1 1 0 0 0 1.50625 1 1 1 1 0 0 0 1.10625 0 1 1 1 0 1 1 1.50000 1 1 1 1 0 1 1 1.10000 0 1 1 1 0 1 0 1.49375 1 1 1 1 0 1 0 1.09375 0 1 1 1 1 0 1 1.48750 1 1 1 1 1 0 1 fault 0 1 1 1 1 0 0 1.48125 1 1 1 1 1 0 0 fault 0 1 1 1 1 1 1 1.47500 1 1 1 1 1 1 1 fault 0 1 1 1 1 1 0 1.46875 1 1 1 1 1 1 0 fault 1 0 0 0 0 0 1 1.46250 0 0 0 0 0 0 1 1.08750 1 0 0 0 0 0 0 1.45625 0 0 0 0 0 0 0 1.08125 1 0 0 0 0 1 1 1.45000 0 0 0 0 0 1 1 1.07500 1 0 0 0 0 1 0 1.44375 0 0 0 0 0 1 0 1.06875 1 0 0 0 1 0 1 1.43750 0 0 0 0 1 0 1 1.06250 1 0 0 0 1 0 0 1.43125 0 0 0 0 1 0 0 1.05625 1 0 0 0 1 1 1 1.42500 0 0 0 0 1 1 1 1.05000 1 0 0 0 1 1 0 1.41875 0 0 0 0 1 1 0 1.04375 1 0 0 1 0 0 1 1.41250 0 0 0 1 0 0 1 1.03750 1 0 0 1 0 0 0 1.40625 0 0 0 1 0 0 0 1.03125 1 0 0 1 0 1 1 1.40000 0 0 0 1 0 1 1 1.02500 1 0 0 1 0 1 0 1.39375 0 0 0 1 0 1 0 1.01875 1 0 0 1 1 0 1 1.38750 0 0 0 1 1 0 1 1.01250 1 0 0 1 1 0 0 1.38125 0 0 0 1 1 0 0 1.00625 1 0 0 1 1 1 1 1.37500 0 0 0 1 1 1 1 1.00000 1 0 0 1 1 1 0 1.36875 0 0 0 1 1 1 0 0.99375 1 0 1 0 0 0 1 1.36250 0 0 1 0 0 0 1 0.98750 1 0 1 0 0 0 0 1.35625 0 0 1 0 0 0 0 0.98125 1 0 1 0 0 1 1 1.35000 0 0 1 0 0 1 1 0.97500 1 0 1 0 0 1 0 1.34375 0 0 1 0 0 1 0 0.96875 1 0 1 0 1 0 1 1.33750 0 0 1 0 1 0 1 0.96250 1 0 1 0 1 0 0 1.33125 0 0 1 0 1 0 0 0.95625 1 0 1 0 1 1 1 1.32500 0 0 1 0 1 1 1 0.95000 1 0 1 0 1 1 0 1.31875 0 0 1 0 1 1 0 0.94375 1 0 1 1 0 0 1 1.31250 0 0 1 1 0 0 1 0.93750 1 0 1 1 0 0 0 1.30625 0 0 1 1 0 0 0 0.93125 1 0 1 1 0 1 1 1.30000 0 0 1 1 0 1 1 0.92500 1 0 1 1 0 1 0 1.29375 0 0 1 1 0 1 0 0.91875 1 0 1 1 1 0 1 1.28750 0 0 1 1 1 0 1 0.91250 1 0 1 1 1 0 0 1.28125 0 0 1 1 1 0 0 0.90625 1 0 1 1 1 1 1 1.27500 0 0 1 1 1 1 1 0.90000 1 0 1 1 1 1 0 1.26875 0 0 1 1 1 1 0 0.89375 1 1 0 0 0 0 1 1.26250 0 1 0 0 0 0 1 0.88750 1 1 0 0 0 0 0 1.25625 0 1 0 0 0 0 0 0.88125 1 1 0 0 0 1 1 1.25000 0 1 0 0 0 1 1 0.87500 1 1 0 0 0 1 0 1.24375 0 1 0 0 0 1 0 0.86875 1 1 0 0 1 0 1 1.23750 0 1 0 0 1 0 1 0.86250 1 1 0 0 1 0 0 1.23125 0 1 0 0 1 0 0 0.85625 1 1 0 0 1 1 1 1.22500 0 1 0 0 1 1 1 0.85000 1 1 0 0 1 1 0 1.21875 0 1 0 0 1 1 0 0.84375 1 1 0 1 0 0 1 1.21250 0 1 0 1 0 0 1 0.83750 1 1 0 1 0 0 0 1.20625 0 1 0 1 0 0 0 0.83125 table 1 C vr10 7-bit vid table with 6.25mv extensio n downloaded from: http:///
ir3084u page 16 of 47 june 1, 2009 hex (vid7:vid0) dec (vid7:vid0) voltage hex (vid7:vid0) dec (vid7:vid0) voltage 00 00000000 fault 40 01000000 1.21250 01 00000001 fault 41 01000001 1.20625 02 00000010 1.60000 42 01000010 1.20000 03 00000011 1.59375 43 01000011 1.19375 04 00000100 1.58750 44 01000100 1.18750 05 00000101 1.58125 45 01000101 1.18125 06 00000110 1.57500 46 01000110 1.17500 07 00000111 1.56875 47 01000111 1.16875 08 00001000 1.56250 48 01001000 1.16250 09 00001001 1.55625 49 01001001 1.15625 0a 00001010 1.55000 4a 01001010 1.15000 0b 00001011 1.54375 4b 01001011 1.14375 0c 00001100 1.53750 4c 01001100 1.13750 0d 00001101 1.53125 4d 01001101 1.13125 0e 00001110 1.52500 4e 01001110 1.12500 0f 00001111 1.51875 4f 01001111 1.11875 10 00010000 1.51250 50 01010000 1.11250 11 00010001 1.50625 51 01010001 1.10625 12 00010010 1.50000 52 01010010 1.10000 13 00010011 1.49375 53 01010011 1.09375 14 00010100 1.48750 54 01010100 1.08750 15 00010101 1.48125 55 01010101 1.08125 16 00010110 1.47500 56 01010110 1.07500 17 00010111 1.46875 57 01010111 1.06875 18 00011000 1.46250 58 01011000 1.06250 19 00011001 1.45625 59 01011001 1.05625 1a 00011010 1.45000 5a 01011010 1.05000 1b 00011011 1.44375 5b 01011011 1.04375 1c 00011100 1.43750 5c 01011100 1.03750 1d 00011101 1.43125 5d 01011101 1.03125 1e 00011110 1.42500 5e 01011110 1.02500 1f 00011111 1.41875 5f 01011111 1.01875 20 00100000 1.41250 60 01100000 1.01250 21 00100001 1.40625 61 01100001 1.00625 22 00100010 1.40000 62 01100010 1.00000 23 00100011 1.39375 63 01100011 0.99375 24 00100100 1.38750 64 01100100 0.98750 25 00100101 1.38125 65 01100101 0.98125 26 00100110 1.37500 66 01100110 0.97500 27 00100111 1.36875 67 01100111 0.96875 28 00101000 1.36250 68 01101000 0.96250 29 00101001 1.35625 69 01101001 0.95625 2a 00101010 1.35000 6a 01101010 0.95000 2b 00101011 1.34375 6b 01101011 0.94375 2c 00101100 1.33750 6c 01101100 0.93750 2d 00101101 1.33125 6d 01101101 0.93125 2e 00101110 1.32500 6e 01101110 0.92500 2f 00101111 1.31875 6f 01101111 0.91875 30 00110000 1.31250 70 01110000 0.91250 31 00110001 1.30625 71 01110001 0.90625 32 00110010 1.30000 72 01110010 0.90000 33 00110011 1.29375 73 01110011 0.89375 34 00110100 1.28750 74 01110100 0.88750 35 00110101 1.28125 75 01110101 0.88125 36 00110110 1.27500 76 01110110 0.87500 37 00110111 1.26875 77 01110111 0.86875 38 00111000 1.26250 78 01111000 0.86250 39 00111001 1.25625 79 01111001 0.85625 3a 00111010 1.25000 7a 01111010 0.85000 3b 00111011 1.24375 7b 01111011 0.84375 3c 00111100 1.23750 7c 01111100 0.83750 3d 00111101 1.23125 7d 01111101 0.83125 3e 00111110 1.22500 7e 01111110 0.82500 3f 00111111 1.21875 7f 01111111 0.81875 table 2 C vr11 7-bit vid table downloaded from: http:///
ir3084u page 17 of 47 june 1, 2009 vid4 vid3 vid2 vid1 vid0 vout (v) 0 0 0 0 0 1.550 0 0 0 0 1 1.525 0 0 0 1 0 1.500 0 0 0 1 1 1.475 0 0 1 0 0 1.450 0 0 1 0 1 1.425 0 0 1 1 0 1.400 0 0 1 1 1 1.375 0 1 0 0 0 1.350 0 1 0 0 1 1.325 0 1 0 1 0 1.300 0 1 0 1 1 1.275 0 1 1 0 0 1.250 0 1 1 0 1 1.225 0 1 1 1 0 1.200 0 1 1 1 1 1.175 1 0 0 0 0 1.150 1 0 0 0 1 1.125 1 0 0 1 0 1.100 1 0 0 1 1 1.075 1 0 1 0 0 1.050 1 0 1 0 1 1.025 1 0 1 1 0 1.000 1 0 1 1 1 0.975 1 1 0 0 0 0.950 1 1 0 0 1 0.925 1 1 0 1 0 0.900 1 1 0 1 1 0.875 1 1 1 0 0 0.850 1 1 1 0 1 0.825 1 1 1 1 0 0.800 1 1 1 1 1 off 4 table 3 C opteron 5-bit vid table downloaded from: http:///
ir3084u page 18 of 47 june 1, 2009 dynamic vid operation the ir3084u can accept changes in the vid code whil e operating and vary the dac voltage accordingly. t he sink/source capability of the vdac buffer amp is pr ogrammed by the external resistor that sets the osc illator frequency (rosc). the slew rate of the voltage at t he vdac pin can be adjusted by an external capacito r between vdac pin and the vosns? pin. a resistor connected i n series with this capacitor is required to compens ate the vdac buffer amplifier. digital vid transitions resu lt in a smooth analog transition of the vdac voltag e and converter output voltage minimizing inrush currents in the input and output capacitors and overshoot o f the output voltage. adaptive voltage positioning (avp) adaptive voltage positioning (avp) is needed to red uce the total output voltage deviations during load transients and to reduce the power dissipation of the load whe n it is drawing high current. the circuitry related to the voltage positioning is shown in figure 8. resistor r setpt is connected between the vdac pin and the vsetpt p in to set the desired amount of fixed offset voltage above or below the dac voltage. the vsetpt pin is internally connected to both the non- inverting input of the voltage error amplifier and an interna l current source, i offset . the magnitude of i offset is programmed by the external resistor that programs t he oscillator frequency (rosc) while the polarity o f i offset is set by the vidsel pin. when the vr10 and vr11 dac tables are selected, the polarity of i offset is positive (current flows into the pin). when the opteron/ath lon64 dac table is selected, the polarity of i offset is negative (current flow out of the pin). the voltage across rsetpt sets the no load offset voltage above or bel ow the vdac voltage. the voltage at the vdrp pin is a buffered version o f the current share bus (iin) and represents the su m of the vdac voltage and the average inductor current of al l the phases. the vdrp pin should be connected to t he fb pin through the resistor rdrp. because the error a mp will regulate the voltage at the fb pin equal to the voltage at the vsetpt pin, a current will flow from the vdrp pin to the fb pin equal to (vdrp?vsetpt) / r drp . when the load current increases, the vdrp voltage w ill increase, additional current will flow through the feedback resistor r fb and the converters output voltage will droop belo w the no load setpoint. the amount of voltage droop can be programmed by the resistor r drp so the converters output impedance meets the load -line specification set by the cpu manufacturer. the offs et and slope of the converters output impedance ar e referenced to vdac and are therefore independent of the exact vdac (vid) setting. due to the difference between vdac and fb, the volt age at the vdrp pin causes additional offset voltag e through rdrp and rfb. the total offset voltage is the sum of the voltage across rvsetpt and the volta ge drop across the rfb resistor at no load. csin- csin+ csin- vdrp ishare phase ic eaout phase ic current sense amplifier ishare ishare ishare ishare ... ... iin vdac vdac + - rfb 10k + - vdac 10k rdrp ioffset + - + - vo rsetpt vsetpt fb vdac error amplifier current sense amplifier control ic vdrp amplifier csin+ figure 8 - adaptive voltage positioning downloaded from: http:///
ir3084u page 19 of 47 june 1, 2009 inductor dcr temperature correction if the thermal compensation of the inductor dcr pro vided by the temperature dependent gain of the curr ent sense amplifier is not adequate, a negative tempera ture coefficient (ntc) thermistor can be used for a dditional correction. the thermistor should be placed close t o the inductor and connected in parallel with the f eedback resistor, as shown in figure 9. the resistor in ser ies with the thermistor is used to reduce the nonli nearity of the thermistor. figure 9 - temperature compensation of inductor dcr remote voltage sensing to compensate for impedance in the ground plane, th e vosns? pin is used for remote ground sensing and connects directly to the load. the vdac voltage is referenced to vosns? to avoid additional error term s or delays related to a separate differential amplifier . the capacitor connecting the vdac and vosns? pins ensure that high speed transients are fed directly into th e error amp without delay. start-up modes the ir3084u has a programmable soft-start function to limit the surge current during converter start-u p. a capacitor connected between the ss/del and lgnd pin s controls soft start timing, over-current protecti on delay, and hiccup mode timing. a charge current of 70a c ontrols the positive slope of the voltage at the ss /del pin. there are two types of start-up possible: vr11 and opteron/athlon64. in vr11 mode, the soft start cir cuitry will set the voltage at the vdac pin to the 1.1v boot vo ltage and the converters output will slowly rise u sing the slew rate set by the capacitor at the ss/del pin until i ts equal to the vdac voltage. after vcore reaches the 1.1v boot voltage there will be a short delay, the vid p ins will be sampled, and the voltage at the vdac pi n and the converters output will increase or decrease to the desired vid setting using the dynamic vid slew rat e. in opteron/athlon64 mode, the soft start sequence will ramp the voltage at the vdac pin directly to the e xternal vid setting using the slew rate set by the capacitor at the ss/del pin without pausing at the 1.1v boot vo ltage. eaout iiniin error amplifier control ic avp amplifier vdrp rsetpt vsetpt + - rdrp rt vdac rfb2 rfb + - ioffset vo downloaded from: http:///
ir3084u page 20 of 47 june 1, 2009 figure 10a depicts the start-up sequence without av p in boot mode ? the vidsel pin is either grounded o r floated. first, the vdac pin is charged to the 1.1 v boot voltage. then, if there are no fault conditi ons, the ss/del capacitor will begin to be charged. initial ly, the error amplifiers output will be clamped lo w until the voltage at the ss/del reaches 1.3v. after the volt age at the ss/del pin rises to 1.3v, the error ampl ifiers output will begin to rise and the converters outpu t voltage will be regulated 1.3v below the voltage at the ss/del pin. the converters output voltage will slowly ra mp to the 1.1v boot voltage. the ss/del voltage wil l continue to increase until it rises above the 3.10v threshol d of the vid delay comparator. when the ss/del volt age exceeds 3.10v, the vid inputs will be sampled and t he vdac pin will transition to the level determined by the vid inputs at the dynamic vid slew rate. when the volt age on the ss/del pin rises above 3.77v the vrrdy d elay comparator will allow the vrrdy signal to be assert ed. ss/del will continue to rise until finally set tling at 3.85v, indicating the end of the start-up sequence. figure 10b depicts the start-up sequence in opteron /athlon64 mode ? vidsel is connected to gnd via a 6 .49k resistor. first, the external vid setting is sampl ed and the vdac pin is set to the desired vid volta ge. then, if there are no fault conditions, the ss/del capacitor will begin to charge. initially, the error amplif iers output will be clamped low until the voltage at the ss/del rise s to 1.3v. after the voltage at the ss/del pin rea ches 1.3v, the error amplifiers output will begin to rise and the converters output voltage will be regulated 1 .3v below the voltage at the ss/del pin. as the voltage at the s s/del pin continues to rise, the converters output voltage will slowly increase until it is equal to the voltage at the vdac pin. when the voltage on the ss/del pin rises above 3.77v the vrrdy delay comparator will allow the vrr dy signal to be asserted. ss/del will continue to rise until finally settling at 3.85v, indicating the end of the start-up sequence. if avp is used , the soft start timing will change slightly becaus e of the resistor from the vdrp amplifier to the error amplifiers fb pin. during startup with avp, the vdrp amplifier will produce a voltage at the f b pin equal to vdac times the resistor divider formed by the dr oop resistor and the feedback resistor from vcore t o the fb pin. to offset the contribution from the vdrp ampl ifier, the voltage at the ss/del pin will have to r ise to beyond 1.3v before the error amplifiers output and vcore begi n to rise. for a dac setting of 1.3v with typical vr11 avp, the error amplifiers output will begin to ris e when the voltage at the ss/del pin reaches approx imately 1.8v. the effect of this offset will be to slightly lengthen the start delay (td1) and shorten the sof t start ramp time (td2). the following table summarizes the differences betw een the 3 modes associated with setting the vidsel pin. in addition to changing the soft start sequence, the n o_cpu code may or may not be ignored during startup and the no_cpu code may or may not be latched. vidsel voltage vid table 1.1v boot voltage during startup? ignore no cpu codes during startup? latch no cpu fault code? gnd (<0.6v) vr10 yes yes yes float (>1.8v) vr11 yes yes yes 6.49k to gnd (0.9v ir3084u page 21 of 47 june 1, 2009 3.85v 1.100v ss/del +12vin 9.1v uvlo vrrdy 3.77v enable (vtt) 1.30v vout power-down start normal operation soft start time 1.6ms (td2) (vcc uvl initiates fault mode) (enable ends fault mode) vr_rdy delay 1.3ms (td4+td5) vid sample delay 1.0ms (td3) start delay 1.8ms (td1) dynamic vid time 200us (td4) 0.85v iin eaoout 3.10v vdac 1.100v 1.100v vdac figure 10a C start-up waveforms with boot mode (vid setting > 1.1v) vid setting 9.1v uvlo ss/del +12vin vout vrrdy 3.77v enable (vtt) 1.30v power-down start normal operation (vcc uvl initiates fault mode) soft start time 1.8ms vr_rdy delay 2.3ms (enable ends fault mode) start delay 1.8ms 0.85v eaoout iin vdac vid setting vid setting figure 10b C opteron/athlon64 start-up waveforms (v id setting=1.1v) downloaded from: http:///
ir3084u page 22 of 47 june 1, 2009 fault modes under voltage lock out, vid = fault, as well as a l ow signal on the enable input immediately sets the fault latch. this causes the eaout pin to drive low which turns off the phase ic drivers. the vrrdy pin also drives low. the ss/del capacitor will discharge down to 0. 215v through a 6.5a current source. if the fault h as cleared when ss/del falls to 0.215v then the fault latch wi ll be reset by the discharge comparator allowing a normal start-up sequence to occur. if a vid = fault condi tion is latched it can only be cleared by cycling p ower to the ir3084u on and off. hiccup over-current protection normal operation restart after ocp ss/del (3.85v during normal operation) vout vrrdy 3.75v iout 1.3v ocp threshold ocp delay normal operation 3.77v discharge voltage (0.215v) figure 11 C over-current protection waveforms (vid = 1.1v for simplicity) over-current protection delay and hiccup mode figure 11 depicts the operating waveforms of the ov er current protection (ocp). a delay is included i f an over- current condition occurs after a successful soft st art sequence. this delay is required because over-c urrent conditions can occur as part of normal operation du e to load transients or vid transitions. if an over -current fault occurs during normal operation it will activate the over-current discharge current of 40a but will no t set the fault latch immediately. if the over-current condition pe rsists long enough for the ss/del capacitor to disc harge below the 100mv offset of the delay comparator, the fault latch will be se, the error amps output will be p ulled low, switching in the phase ics will be inhibited, and t he vrrdy signal will be de-asserted. the ss/del capacitor will continue to discharge unt il it reaches 0.215v and the fault latch is reset a llowing a normal soft start to occur. if an over-current con dition is again encountered during the soft start c ycle the fault latch will be set without any delay and hiccup mode will begin. during hiccup mode the 11.2 to 1 charg e to discharge current ratio results in a 9% hiccup mode duty cycle regardless of at what point the over-cu rrent condition occurs. if the ss/del pin is pulled below 0.85v, the conver ter can be disabled. downloaded from: http:///
ir3084u page 23 of 47 june 1, 2009 under voltage lockout (uvlo) the uvlo function monitors the ir3084us vcc supply pin and ensures that there is adequate voltage to safely power the internal circuitry. the ir3084us uvlo is set higher than the minimum operating voltage of c ompatible phase ics thus providing uvlo protection for them a s well. uvlo at the phase ics is a function of the error amplifiers output voltage. when the ir3084u is in uvlo, the error amplifier is disabled and eaout is at a very low voltage (<200mv) thus preventing the phase ics from becoming active. during power-up the fault latch will be reset when vcc exceeds 9.9v and there are no other faults. if the vcc voltage drops below 9.1v the fault latch will be se t. over current protection (ocp) the current limit threshold is set by a resistor co nnected between the ocset and vdac pins. if the iin pin voltage, which is proportional to the average phase current plus dac voltage, exceeds the ocset voltag e, the over-current protection is triggered. vid = fault code (no_cpu) when vidsel is grounded or left floating, no_cpu vi d codes of 11111xx for vr10 and 0000000x, 1111111x for vr11 will set both the vid fault latch and the fault latch to disable the error amplifier. the co ntroller will be latched off and a power-on reset (por) must be perf ormed to produce a new soft start sequence. in the se 2 modes, the no_cpu codes are ignored during startup. see table 1 for further details. when vidsel is connected to gnd via a 6.49k resisto r, no_cpu vid codes of 11111 will set the fault lat ch to disable the error amplifier but the vid fault latch will not be set. the controller will not be latch ed off and a soft start sequence will be produced when the no_cp u code is removed and the ss/del voltage falls belo w 0.215v. in opteron/athlon64 mode, the no_cpu codes are not ignored during startup. see table 1 for f urther details. a 1.3s delay is provided to prevent a no_cpu fault condition from occurring during dynamic vid change s. vr_rdy (power good) output the vrrdy pin is an open-collector output and shoul d be pulled up to a voltage source through a resist or. during soft start, the vrrdy remains low until the output voltage is in regulation and ss/del is above 3.77v. the vrrdy pin becomes low if the fault latch is set . a high level at the vrrdy pin indicates that the converter is in operation and has no fault, but does not ensure the output voltage is within the specification. out put voltage regulation within the design limits can logically b e assured however, assuming no component failure in the system. load current indicator output the vdrp pin voltage represents the average phase c urrent of the converter plus the dac voltage. the l oad current can be retrieved by subtracting the vdac vo ltage from the vdrp voltage. downloaded from: http:///
ir3084u page 24 of 47 june 1, 2009 system reference voltage (vbias) the ir3084u supplies a 6.8v/6ma precision reference voltage from the vbias pin. the oscillator ramp tr ip points are based on the vbias voltage so it should be used to program the phase ics phase delay to minimize p hase errors. phase ic gate driver bias regulator / vrhot compara tor an internal amplifier can be configured as a gate d river bias regulator to provide programmable gate d river voltage for phase ics (figure 12a), or a thermal mo nitor to provide vrhot/vrfan signal as required in vr11 (figure 12b). the internal current source iregset whose value is programmed by the switching frequency going through the external rset resistor sets the gate driver voltage or the vrhot/vrfan threshold voltage. an ntc therm istor is used to monitor the temperature on the vrm/vrd. 10nf cvgdrv ir3084 control ic + - q1 cjd200 regdrv 1ohm / 1206 rpu 97.6k rvgdrv + 10uf c2 regfb iregset 0adc regset vcc +12v vgdrive figure 12a C ir3084u bias regulator configured for gate driver bias regulator 10k r1 3k r3 r2 100k regdrv ir3084 control ic + - iregset vcc regset 10nf c2 2n7002 q5 vrhot# 1k r5 2k r4 1.1meg rh1 regfb 1nf c1 2k rpu1 +3.3v vbias 36k rh2 figure 12b C ir3084u bias regulator configured for vrhot/vrfan function downloaded from: http:///
ir3084u page 25 of 47 june 1, 2009 performance characteristics figure 13: oscillator frequency versus rosc 100 200 300 400 500 600 700 800 900 1000 10 20 30 40 50 60 70 80 90 rosc (kohms) oscillator frequency (khz) figure 14: i(ocset) versus rosc 10 20 30 40 50 60 70 80 90 100 110 120 10 20 30 40 50 60 70 80 90 rosc (kohms) ua figure 15: i(vsetpt) versus rosc 10 20 30 40 50 60 70 80 90 100 110 120 10 20 30 40 50 60 70 80 90 rosc (kohms) ua figure 16: i(regset) current versus rosc 10 30 50 70 90 110 130 150 170 190 210 230 250 10 20 30 40 50 60 70 80 90 rosc (kohms) ua figure 17: vdac sink & source current vs. rosc 20 40 60 80 100 120 140 160 180 200 220 240 260 10 20 30 40 50 60 70 80 90 rosc (kohms) ua i(vdac source) (ua) i(vdac sink) (ua) figure 18: ir3084 error amplifier bode plot -50 0 50 100 150 200 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 frequency (hz) gain (db) and phase (deg) gain phase downloaded from: http:///
ir3084u page 26 of 47 june 1, 2009 applications information 0.1uf 0.1uf ccs+ rphase1 dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086 phase ic rphase2 rbiasin rcs- ccs- cpwmrmp 0.1uf rphase3 cscomp rpwmrmp rcs+ 0.1uf 0.1uf ccs+ rphase1 dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086 phase ic rphase2 rbiasin rcs- ccs- cpwmrmp 0.1uf rphase3 cscomp rpwmrmp rcs+ 0.1uf 0.1uf ccs+ rphase1 dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086 phase ic rphase2 rbiasin rcs- ccs- cpwmrmp 0.1uf rphase3 cscomp rpwmrmp rcs+ +12v cin vrhot vr ready vout sense+ vout+ phase fault vout sense- rosc 30.1k rocset 12.7k rvsetpt2 124 css/del 0.1uf rfb 162 c90 100pf rcp 2.49k rdrp1 750 cfb 12nf cout distribution impedance ccp 100pf outen +5.0v vid0 vid1 vid3 vid2 rvgdrv 97.6k vid4 vid5 vid6 vid7 +12v ccp 56nf r138 2k vid_sel r118 1.21k cvgdrv 10nf cvdac 33nf rvdac 3.5 c1010 100pf r31 10 c131 0.1uf c136 0.1uf vid5 4 vid0 9 vid1 8 vid2 7 vid3 6 vid4 5 rmpout 19 lgnd 22 vdac 12 ss/del 26 enable 28 vosns-- 10 fb 17 regdrv 24 rosc 11 regset 25 vdrp 16 iin 15 eaout 18 vcc 21 vid6 3 intl_md 2 vrrdy 27 vsetpt 14 vidsel 1 vbias 20 regfb 23 ocset 13 u 6 ir3084umtr rfb 348 rt 4.7k, b=4450 c205 0.1uf q8 cjd200 r1332 1 c137 1uf 0.1uf 0.1uf ccs+ rphase1 dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086 phase ic rphase2 rbiasin rcs- ccs- cpwmrmp 0.1uf rphase3 cscomp rpwmrmp rcs+ 0.1uf 0.1uf ccs+ rphase1 dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086 phase ic rphase2 rbiasin rcs- ccs- cpwmrmp 0.1uf rphase3 cscomp rpwmrmp rcs+ rvsetpt1 750 rdrp2 figure 19 C ir3084u/3086 5 phase vrm/evrd 11 conver ter downloaded from: http:///
ir3084u page 27 of 47 june 1, 2009 design procedures ? ir3084u and ir3086 chipset ir3084u external components oscillator resistor rosc the oscillator of ir3084 generates a triangle wavef orm to synchronize the phase ics, and the switching frequency of the each phase converter equals the os cillator frequency, which is set by the external re sistor r osc according to the curve in figure 13 on page vdac slew rate programming capacitor c vdac and resistor r vdac the sink and source currents of the vdac pin are se t by the value of r osc . the sink current capability of the vdac pin is slightly less than the source current. therefore, the vdac sink current (i sink ) should be used to calculate c vdac to insure that the dynamic vid slew rate when vcor e decreases is not too slow. the negative slew rate of vdac (sr down ) is programmed by the external capacitor c vdac as shown in equation (1). the resistor r vdac is used to compensate/stabilize the vdac circuit a nd is determined by equation (2). the positive slew rate of the vdac voltage (sr up ) is proportional to the negative slew rate of vdac and can be calculated using equation (3). down sink vdac sr i c = (1) where: i sink is the sink current of the vdac pin at the chosen value of r osc as shown in figure 17 on page 25. 2 15 10 2.3 5.0 vdac vdac c r ? ? + ? = (2) vdac source up c i sr = (3) where: i source is the source current of the vdac pin at the chose n value of r osc as shown in figure 17 on page 25. the vid voltage rise or fall time during startup wi th boot mode (td4) can be calculated using either e quation (4a) or (4b). ( ) v vdac i c td source vdac 1.1 4 ? ? = if vdac > 1.1v (4a) ( ) vdac v i c td sink vdac ? ? = 1.1 4 if vdac < 1.1v (4b) where: vdac is the dac voltage set by the vid pins . i source and i sink are the source and sink currents of the vdac pin. if boot mode is not used then td4 = 0. downloaded from: http:///
ir3084u page 28 of 47 june 1, 2009 no load output voltage setting resistor r vsetpt , feedback resistor rfb, and avp resistor r drp an external resistor, r vsetpt , connected between the vdac pin and the vsetpt pin is used to set the no load output voltage offset, v o_nlofst , which is the difference between the v dac voltage and output voltage at no load. however, the converters output voltage will be set by the combination of vsetpt plus some contributio n from the vdrp pin. at no load, both pins of the error a mplifier are at vdac C vsetpt while the vdrp pin is at vdac + v cs_ofst g csa (v cs_ofst and g csa are the input offset and gain of the current sense amplifiers). because the vdrp pin is at a higher voltage than the fb pin of the error amplifier, vdrp will contribute to th e no load offset through the rdrp and rfb resistors. the des ign approach is to choose a value for the feedback resistor, rfb, from 100 to 2k and then calculate rdrp and r vsetpt to provide the required no load offset voltage. d) c b (a b c d a vsetpt ? ? + ? = * * (5) csa tofst cs csa l g v n g r io a * * * _ + = csa tofst cs g v c * _ = ro io v b o_nlofst * + = o_nlofst v d = where : i o is the full load output current of the converter r l is the dcr of the output inductor g csa is the gain of the current sense amplifiers n is the number of phases v o_nlofst is the no load offset voltage below the dac setting, a positive number for vr10 and vr11, a negative n umber for amd ro is the desired load line slope (ohms) v cs_tofst is the total offset voltage of the current sense a mplifiers, see below. the total input offset voltage (v cs_tofst ) of the current sense amplifier in the phase ic is the sum of input offset (v cs_ofst) of the amplifier itself plus that created by the a mplifier input bias currents flowing through the cu rrent sense resistors r cs+ and r cs? as shown in equation (6). ( ) ( ) ? ? + + ? ? ? + = cs csin cs csin cs_ofst cs_tofst r i r i v v (6) finally, calculate the no-load setpoint resistor us ing equation (7) and the droop resistor using equat ion (8); vsetpt i vsetpt rvsetpt = (7) where : i vsetpt is the current into the vsetpt pin at the switchin g frequency, which is a function of r osc . see figure 15 on page 25. vsetpt is calculated by equation (5). vsetpt d c vsetpt rfb rdrp ? + ? = (8) downloaded from: http:///
ir3084u page 29 of 47 june 1, 2009 soft start capacitor c ss/del and resistor r ss/del because the capacitor c ss/del programs three different time parameters, i.e. sof t start time, over current latch delay time, and the frequency of hiccup mode, they should be considered together while choosing c ss/del . the soft-start ramp time (td2) is the time required for the converters output voltage to rise from 0v to the dac voltage (vdac). given a desired soft-start ramp ti me (td2) and the soft-start charge current (i chg ) from the data sheet, the value of the external capacitor (c ss/del ) can be calculated using equation (9). + ? ? = + ? ? = ? rdrp rfb rfb vdac td rdrp rfb rfb vdac td i c chg del ss 1 2 * 10 * 70 1 2 * 6 / (9) where: vdac = 1.1v in boot mode or the dac voltage set by the vid pins without boot mode. rfb is the resistor from vcore to the fb pin of th e controller. rdrp is the resistor from vdrp to fb. if droop is not used, set the second term within th e parenthesis to zero (rdrp = ). once c ss/del is determined, the soft start delay time td1, the vid sample time td3, the vrrdy delay time td5, and the over-current fault latch delay time t ocdel are determined and can be calculated using equatio ns (10), (11), (12), and (13) respectively. + ? + ? = rdrp rfb rfb vdac v i c td chg del ss 3.1 1 / (10) where: vdac = 1.1v in boot mode or the dac voltage set by the vid pins without boot mode. ichg is the soft-start charge current, nominally 7 0a. rfb is the resistor from vcore to the fb pin of th e controller. rdrp is the resistor from vdrp to fb. if droop is not used, set the second term within th e parenthesis to zero (rdrp = ). ( ) v c v v v i c td del ss chg del ss 7.0 10 * 70 1.1 3.1 1.3 3 6 / / ? = ? ? ? = ? (11) if boot mode is not used, then td3 is zero. 4 10 * 70 75.0* 4 ) 1.3 85.3(* 5 6 / / td v c td i v v c td del ss chg del ss ? = ? ? = ? (12) where: td4 is the vid voltage rise time calculated from equation 4. 6 / _ / 10 * 40 100 * 100 * ? = = mv c i mv c t del ss dischg oc del ss ocdel (13) where: i oc_dischg is the over-current discharge current of the ss/del pin from the data sheet. downloaded from: http:///
ir3084u page 30 of 47 june 1, 2009 over current setting resistor r ocset the inductor dc resistance is utilized to sense the inductor current. the copper wire of the inductor has a constant temperature coefficient of 3850 ppm, and t herefore the maximum inductor dcr can be calculated from equation (14), where r l_max and r l_room are the inductor dcr at maximum temperature t l_max and room temperature t_ room respectively. )] t (t 3850*10 [1 r r room l_max 6 l_room l_max ? ? + ? = ? (14) the current sense amplifier gain of the ir3086a dec reases with temperature at the rate of 1470 ppm, wh ich compensates part of the inductor dcr increase. the phase ic die temperature is only a couple of degree s celsius higher than the pcb temperature due to the low thermal impedance of mlpq package. the minimum current sense amplifier gain at the maximum phase i c temperature t ic_max is calculated from equation (15). )] t (t 1470*10 [1 g g room ic_max 6 cs_room cs_min ? ? ? ? = ? (15) the over-current limit is set by the external resis tor r ocset as defined in equation (16), where i limit is the required over current limit. i ocset, the bias current of the ocset pin, changes with sw itching frequency setting resistor r osc and is determined by the curve in figure 14 on pag e 25. k p is the ratio of inductor peak current to average current in each phase and is calculated fro m equation (17). ocset min cs cs_tofst p l_max limit ocset i g ] v ) k (1 r n i [ r _ ? + + ? ? = (16) /n i 2) f v /(l v ) v (v k limit sw i fl o fl o i p ? ? ? ? ? = _ _ (17) where: v i is the input voltage to the converter (nominally 1 2v). v o_fl is the output voltage of the converter with droop at the over-current threshold. l is the value of the output inductors. f sw is the switching frequency. i limit is the dc output current of the converter when the over-current fault occurs. n is the number of phases. downloaded from: http:///
ir3084u page 31 of 47 june 1, 2009 ir3086 external components pwm ramp resistor r pwmrmp and capacitor c pwmrmp pwm ramp is generated by connecting the resistor r pwmrmp between a voltage source and pwmrmp pin as well as the capacitor c pwmrmp between pwmrmp and lgnd. choose the desired pwm ra mp magnitude v ramp and the capacitor c pwmrmp in the range of 100pf and 470pf, and then calculate the resistor r pwmrmp from equation (18). to achieve feed?forward voltage mode control, the resistor r ramp should be connected to the input of the converter. )] pwmrmp v dac v in ln(v ) dac v in *[ln(v pwmrmp *c sw *f in v o v pwmrmp r ? ? ? ? = (18) inductor current sensing capacitor c cs+ and resistors r cs+ and r cs? the dc resistance of the inductor is utilized to se nse the inductor current. usually the resistor r cs+ and capacitor c cs+ in parallel with the inductor are chosen to match the time constant of the inductor, and therefore th e voltage across the capacitor c cs+ represents the inductor current. if the two time c onstants are not the same, the ac component of the capacitor voltage is different fro m that of the real inductor current. the time const ant mismatch does not affect the average current sharing among t he multiple phases, but affect the current signal i share as well as the output voltage during the load current transient if adaptive voltage positioning is adopte d. measure the inductance l and the inductor dc resist ance r l . pre?select the capacitor c cs+ and calculate r cs+ as follows. + + = cs l cs c r l r (19) the bias current flowing out of the non-inverting i nput of the current sense amplifier creates a volta ge drop across r cs+, which is equivalent to an input offset voltage of t he current sense amplifier. the offset affects the accuracy of converter current signal ishare as well as the a ccuracy of the converter output voltage if adaptive voltage positioning is adopted. to reduce the offset voltag e, a resistor r cs? should be added between the amplifier inverting input and the converter output . the resistor r cs? is determined by the ratio of the bias current from the non-inverting input and the bias current from the i nverting input. + ? + ? ? = cs csin csin cs r i i r (20) if r cs? is not used, r cs+ should be chosen so that the offset voltage is sma ll enough. usually r cs+ should be less than 2 k and therefore a larger c cs+ value is needed. downloaded from: http:///
ir3084u page 32 of 47 june 1, 2009 over temperature setting resistors r hotset1 and r hotset2 the threshold voltage of vrhot comparator is propor tional to the die temperature t j (oc) of phase ic. determine the relationship between the die temperat ure of phase ic and the temperature of the power co nverter according to the power loss, pcb layout and airflow etc, and then calculate hotset threshold voltage corresponding to the allowed maximum temperature fr om equation (21). 1.241 *t 4.73*10 v j 3 hotset + = ? (21) there are two ways to set the over temperature thre shold, central setting and local setting. in the ce ntral setting, only one resistor divider is used, and the setting voltage is connected to hotset pins of all the phas e ics. to reduce the influence of noise on the accuracy of ov er temperature setting, a 0.1uf capacitor should be placed next to hotset pin of each phase ic. in the local s etting, a resistor divider per phase is needed, and the setting voltage is connected to hotset pin of each phase. t he 0.1uf decoupling capacitor is not necessary. use vbias as the reference voltage. if r hotset1 is pre?selected, r hotset2 can be calculated as follows. hotset bias hotset hotset1 hotset2 v v v r r ? ? = (22) phase delay timing resistors r phase1 and r phase2 the phase delay of the interleaved multiphase conve rter is programmed by the resistor divider connecte d at rmpin+ or rmpin? depending on which slope of the os cillator ramp is used for the phase delay programmi ng of phase ic, as shown in figure 4. if the positive slope is used, rmpin+ pin of the ph ase ic should be connected to rmpout pin of the con trol ic and rmpin? pin should be connected to the resistor divider. when rmpout voltage is above the trip volt age at rmpin? pin, the pwm latch is set. gatel becomes low , and gateh becomes high after the non-overlap time . if the negative slope is used, rmpin? pin of the ph ase ic should be connected to rmpout pin of the con trol ic and rmpin+ pin should be connected to the resistor divider. when rmpout voltage is below the trip volt age at rmpin? pin, the pwm latch is set. gatel becomes low , and gateh becomes high after the non-overlap time . it is best to use the vbias voltage as the referenc e for the resistor dividers because the oscillator ramp magnitude from the control ic will track the vbias voltage. it is best to avoid the peak and valley of the oscillator ramp for better noise immunity. determine the ratio of the programming resistors corresponding to the desired switching frequencies and phase numbers. if the res istor r phasex1 is pre-selected, the resistor r phasex2 is determined as: phasex phasex1 phasex phasex2 ra 1 r ra r ? ? = (23) downloaded from: http:///
ir3084u page 33 of 47 june 1, 2009 combining the over temperature and phase delay sett ing resistors r phase1 , r phase2 and r phase3 the over temperature setting resistor divider can b e combined with the phase delay resistor divider to save one resistor per phase. calculate the hotset threshold voltage v hotset corresponding to the allowed maximum temperature f rom equation (20). if the over temperature setting volt age is lower than the phase delay setting voltage, vbias*ra phasex , connect rmpin+ or rmpin? pin between r phasex1 and r phasex2 and connect hotset pin between r phasex2 and r phasex3 respectively. pre-select r phasex1, then calculate r phasex2 and r phasex3 , ) ra (1 v )*r v v (ra r phasex bias phasex1 hotset bias phasex phasex2 ? ? ? ? = (24) ) ra *(1 v r v r phasex bias phasex1 hotset phasex3 ? ? = (25) if the over temperature setting voltage is higher t han the phase delay setting voltage, vbias*ra phasex , connect hotset pin between r phasex1 and r phasex2 and connect rmpin+ or rmpin? between r phasex2 and r phasex3 respectively. pre-select r phasex1 , hotset bias phasex1 bias phasex hotset phasex2 v v r ) v ra (v r ? ? ? ? = (26) hotset bias phasex1 bias phasex phasex3 v v *r v ra r ? ? = (27) bootstrap capacitor c bst depending on the duty cycle and gate drive current of the phase ic, a 0.1uf to 1uf capacitor is needed for the bootstrap circuit. decoupling capacitors for phase ic 0.1uf?1uf decoupling capacitors are required at vcc and vccl pins of phase ics. downloaded from: http:///
ir3084u page 34 of 47 june 1, 2009 voltage loop compensation the adaptive voltage positioning is used in the com puter applications to meet the load line requiremen ts. like current mode control, the adaptive voltage position ing loop introduces extra zero to the voltage loop and splits the double poles of the power stage, which make the vol tage loop compensation much easier. resistors r fb and r drp are chosen according to equations (15) and (16), a nd the selection of compensation type depends on the capacitors used. for the appli cations using electrolytic, polymer or al?polymer c apacitors, type ii compensation shown in figure 20 (a) is usua lly adequate. while for the applications with only ceramic capacitors, type iii compensation shown in figure 2 0 (b) is preferred. rcp ccp1 eaout ccp rfb rdrp vo+ vdrp vdac + - eaout fbfb cfb cdrp rcp eaout ccp1 ccp rfb rdrp vo+ vdrp vdac fb + - eaout rfb1 (a) type ii compensation (b) type iii compensation figure 20: voltage loop compensation networks type ii compensation determine the compensation at no load, the worst ca se condition. choose the crossover frequency fc bet ween 1/10 and 1/5 of the switching frequency per phase. assume the time constant of the resistor and capaci tor across the output inductors matches that of the inductor, r cp and c cp can be determined by equations (28) and (29). 2 ce e c o pwmrmp fb e e 2 c cp ) r c f (2 1 v v r c l )f (2 r * * * * * * * * * + = (28) cp e e cp r c l 10 c * * = (29) where l e and r ce are the equivalent output inductance and esr of th e output capacitors, respectively. c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency nois e. a ceramic capacitor between 10pf and 220pf is usually enough. downloaded from: http:///
ir3084u page 35 of 47 june 1, 2009 type iii compensation determine the compensation at no load, the worst ca se condition. choose the crossover frequency fc bet ween 1/10 and 1/5 of the switching frequency per phase. assume the time constant of the resistor and capaci tor across the output inductors matches that of the inductor, r cp and c cp can be determined by equations (30) and (31), where c e is equivalent output capacitance. o pwmrmp e e 2 c cp v v c l )f (2 r * * * * = (30) cp e e cp r c l 10 c * * = (31) choose resistor r fb1 according to equation (33), and determine c fb and r drp from equations (32) and (33). fb fb1 r 2 1 r * = to fb fb1 r 3 2 r * = (32) fb1 c1 fb r f 4 1 c * * = (33) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usual ly enough. current share loop compensation the crossover frequency of the current share loop s hould be at least one decade lower than that of the voltage loop in order to eliminate the interaction between the two loops. a capacitor from scomp to lgnd is us ually enough for most of the applications. choose the cro ssover frequency of current share loop (f ci ) based on the crossover frequency of voltage loop (f c ), and determine the c scomp , 6 ci o mi o o e ci le cs_room o i pwmrmp scomp 10 1.05 f 2 v f )] i v( c f 2 [1 r g i v r 0.65 c * * * * * * * * * * * * * * + = (34) where fmi is the pwm gain in the current share loop , ) v (v ) v v (v v f c r fmi dac i dac pwmrmp o pwmrmp sw pwmrmp pwmrmp ? ? ? = * * * * (35) downloaded from: http:///
ir3084u page 36 of 47 june 1, 2009 design example: vrm 11 7?phase converter specifications input voltage: v i = 12v dac voltage: v dac = 1.3v no load output voltage offset: v o_nlofst = 15mv output current: i o = 130 adc maximum output current: i omax = 150 adc load line slope: r o = 1.20 m vrm11 startup boot voltage = 1.100v soft start time: td2 = 1.1ms vcc ready to vcc power good delay: td5 = 1.0ms over current delay: t ocdel = 250s dynamic vid negative slew rate: sr down = 2.5mv/us over temperature threshold: t pcb = 115 oc power stage phase number: n = 7 switching frequency: f sw =400 khz output inductors: l = 220 nh, r l = 0.60 m output capacitors: c = 560uf, r c = 7m , number cn = 10 ir3084 external components oscillator resistor rosc the switching frequency sets the value of r osc as shown by the curve in figure 13 on page 25. in this design, the switching frequency of 400khz per phase require s r osc to be 30.1k . vdac slew rate programming capacitor c vdac and resistor r vdac from figure 17 on page 25, the sink current of the vdac pin at 400khz (r osc =30.1k ) is 80ua. calculate the vdac slew-rate programming capacitor from the speci fied negative slew rate using equation (1). nf sr i c down sink vdac 0.32 10/ 10 *5.2 10 * 80 6 3 6 = = = ? ? ? , choose c vdac = 33nf calculate the vdac compensation resistor from equat ion (2); 3.5 ) (33*10 3.2*10 0.5 c 3.2*10 0.5 r 29 15 2 vdac 15 vdac = + = + = ? ? ? from figure 17 on page 25, the source current of th e vdac pin is 90ua at r osc = 30.1k . the vdac positive slew rate is can be calculated using equation (3); 2.7mv/us 33*10 90*10 c i sr 9 6 vdac source up = = = ? ? downloaded from: http:///
ir3084u page 37 of 47 june 1, 2009 using the calculated value of c vdac , find the positive vid voltage rise time (td4) to the specified nominal dac voltage of 1.300v during startup with boot mode usi ng equation 4a; ( ) ( ) us v v ua nf v vdac i c td source vdac 3.73 1.1 300 .1* 90 33 1.1 4 = ? = ? ? = no load output voltage setting resistor rvsetpt, r fb and adaptive voltage positioning resistor r drp first, use equations (19) and (20) to calculate the current sense resistors r cs+ and r cs? , respectively. for this design, in the next section, r cs+ is determined to be 10k and r cs? is found to be 6.19k . second, calculate the total input offset voltage (v cs_tofst ) of the current sense amplifiers using equation (6 ). from the ir3086a data sheet, typical values for the i csin+ and i csin? bias currents are determined to be 0.25a and 0.40a, respectively. ( ) ( ) ? ? + + ? ? ? + = cs csin cs csin cs_ofst cs_tofst r i r i v v ( ) ( ) mv k k mv 574 .0 19.6* 10 * 40.0 10 * 10 * 25.0 55.0 6 6 = ? ? ? + = ? ? next, derive the intermediate calculations (a,b,c,d ) as shown below before finally calculating r vsetpt and rdrp using equations (7) and (8). from figure 15 on pag e error! bookmark not defined. , the i vsetpt bias current is determined to be 40a at r osc =30.1k and a typical value for the offset voltage of the error amplifier is 0.0mv. mv v g v n g r io a ea os csa tofst cs csa l 0.0 34 * 10 * 574 .0 7 34 * 10 * 60.0* 130 * * * 3 3 _ _ + + = + + = ? ? 3984 .0 = 1710 .0 0.0 10 * 20.1* 130 10 * 15 * 3 3 _ _ = ? + = ? + = ? ? mv v ro io v b ea os nlofst o 0.0.0195 0.0mv *34 0.574*10 v *g v c 3 os_ea csa cs_tofst = + = + = ? 015 .0 0.0 10 * 15 3 _ _ = ? = ? = ? mv v v d ea os nlofst o v d c b a b c d a vsetpt 00494 .0 015 .0 0195 .0 1710 .0 3984 .0 1710 .0* 0195 .0 015 .0* 3984 .0 ) ( * * = ? ? + ? = ? ? + ? = ohms x i vsetpt rvsetpt vsetpt 5. 123 10 40 00494 .0 6 = = = ? choose the closest standard resistor value to this with 1% tolerance or rvestpt = 124ohms. downloaded from: http:///
ir3084u page 38 of 47 june 1, 2009 select rfb = 324 ohms and then calculate the droop resistor, ohms vsetpt d c vsetpt rfb rdrp 1. 787 00494 . 0 015 . 0 0195 .0 00494 .0 324 = ? + ? = ? + ? = choose the next standard value higher than this with 1% tolerance or rdrp = 787ohms. soft start capacitor c ss/del and startup times calculate the soft start capacitor from the require d soft start time using equation (9) with boot mode ; 0.1uf or 0988 .0 787 324 324 1 * 1.1 10 *1.1* 10 * 70 1 2 * 10 * 70 3 6 6 / uf v rdrp rfb rfb vdac td c del ss = + ? = + ? ? = ? ? ? the soft start delay time can be calculated using e quation (10) with boot mode; + + = + ? + ? = ? ? 787 324 324 * 1.1 3.1 * 10 * 70 10 *1.0 6 6 v v rdrp rfb rfb vdac 1.3v i c td1 chg ss/del ms 31.2 = the vid sample time can be found using equation (11 ); ms i v c td chg del ss 00.1 10 * 70 7.0 10 *1.0 7.0 3 6 6 / = ? = ? = ? ? the power good delay time can be found using equati on (12); ms us v td i v c td chg del ss 998 .0 73 10 * 70 75.0* 10 *1.0 4 75.0* 5 6 6 / = ? = ? = ? ? finally, use equation (13) to calculate the over-cu rrent fault latch delay time; us mv c t del ss ocdel 250 10 * 40 10 * 100 * 10 *1.0 10 * 40 100 * 6 3 6 6 / = = = ? ? ? ? downloaded from: http:///
ir3084u page 39 of 47 june 1, 2009 over current setting resistor r ocset assume that room temperature is 25oc and the target pcb temperature is 100 oc. the phase ic die temper ature is usually about 1 oc higher than that of phase ic and the inductor temperature is close to pcb temper ature. calculate the inductors dc resistance at 100 oc us ing equation (14); ? = ? ? + ? = ? ? + ? = ? ? ? m 25)] (100 3850*10 [1 *10 0. )] t (t 3850*10 [1 r r 6 3 room l_max 6 l_room l_max 77.0 60 the current sense amplifier gain is 34 at 25oc, and its gain at 101oc is calculated using equation (15 ), 2 30. 25)] (101 1470*10 [1 34 )] t (t 1470*10 [1 g g 6 room ic_max 6 cs_room cs_min = ? ? ? ? = ? ? ? ? = ? ? here we will set the over current shutdown threshol d to 155a at maximum operating temperature. from f igure 14 on page error! bookmark not defined. , the bias current of the ocset pin (i ocset ) is 42.5a with r osc =30.1k . the total current sense amplifier input offset vo ltage calculated previously is 0.574mv, which includes the offset created by the current sense am plifier input resistor mismatch. calculate the constant k p, the ratio of inductor peak current over average cur rent in each phase using equation (17); 273 .0 7/ 155 )2 10 * 400 12 10 * 220 /( 18.1 )18.1 12( / )2 /( ) ( 3 9 = ? ? ? ? ? = ? ? ? ? ? = ? n i f v l v v v k limit sw i o o i p finally, calculate the over-current setting resisto r using equation (16); ocset min cs cs_tofst p l_max limit ocset i g ] v ) k (1 r n i [ r _ ? + + ? ? = ( ) ? = ? + + ? ? = ? ? ? 15.8k 10 * 5 . 42 2.30 ) 10 * 574 .0 273 .0 1 10 * 77.0 7 155 ( 3 3 3 downloaded from: http:///
ir3084u page 40 of 47 june 1, 2009 ir3086 phase ic components pwm ramp resistor r ramp and capacitor c ramp set the pwm ramp magnitude v pwmrmp to 0.8v. choose 220pf for the pwm ramp capacitor c pwmrmp and calculate the resistor r pwmrmp using equation (18); )] v v ln(v ) v [ln(v c f v v r pwmrmp dac in dac in pwmrmp sw in o pwmrmp ? ? ? ? ? ? ? = 15.8k 0.8)] 1.30 ln(12 1.30) [ln(12 220*10 400*10 12 1.30 12 3 = ? ? ? ? ? ? ? = ? , choose a standard resistor value, r pwmrmp =15.8k . inductor current sensing capacitor c cs+ and resistors r cs+ and r cs? choose c cs+ =47nf and calculate r cs+ using equation (19); 10.0k 10 * 47 ) 10 * /(0.47 10 * 220 c r l r 9 3 9 cs l cs = = = ? ? ? + + the bias currents of csin+ and csin? are 0.25ua and 0.4ua respectively. calculate resistor r cs? using equation (20); ? = ? = ? = + ? k r r cs cs 2.6 10 *0.10 4 . 0 25.0 4 . 0 25.0 3 , choose r cs? = 6.19k over temperature setting resistors r hotset1 and r hotset2 use central over temperature setting and set the te mperature threshold at 115 oc, which corresponds th e ic die temperature of 116 oc. calculate the hotset thresho ld voltage corresponding to the temperature thresho lds using equations (21) and (22); v t v j hotset 79.1 241 .1 116 10 * 73.4 241 .1 * 10 * 73.4 3 3 = + ? = + = ? ? , choose r hotset1 =20.0k , ? = ? ? = ? ? = k v v v r r hotset bias hotset hotset hotset 14.7 79.1 8.6 79.1 10 * 20 3 1 2 downloaded from: http:///
ir3084u page 41 of 47 june 1, 2009 phase delay timing resistors rphasex1 to rphasex2 ( x =1,2,?,7) the phase delay resistor ratios for phases 1 to 7 a t 400khz are (from the x?phase excel based design spreadsheet); raphase1=0.580, raphase2=0.397, rapha se3=0.215, raphase4=0.206, raphase5=0.353 raphase6=0.5 and raphase7=0.647. pre?select rphase11=rphase21=rphase31=rphase41=rpha se51=rphase61=rphase71=20k , ? = ? ? = ? ? = k r ra ra r phase phase phase phase 6.27 10 * 20 58.0 1 58.0 1 3 11 1 1 12 calculating the other resistors from the same formu la results in; r phase22 =13.2k , r phase32 =5.48k , r phase42 =5.2k , p phase52 =10.9k , r phase62 =20k , r phase72 =36.6k . phase ics 1?3 should have the rmpout voltage from t he 3084 controller connected to their rmpin? pin so they will trigger on the negative slope of the rmpo ut waveform. phase ics 4?7 should have the rmpout voltage from the 3084 controller connected to their rmpin+ pin so they will trigger on the positive sl ope of the rmpout waveform. bootstrap capacitor c bst choose c bst =0.1uf. decoupling capacitors for phase ic and power stage choose c vcc =0.1uf, c vccl =0.1uf voltage loop compensation al?polymer output capacitors are used in the design , for instructional purposes type iii compensation as shown in figure 18(b) will be demonstrated here. first, choose the desired crossover frequency as 1/10 of t he switching frequency, f c =40 khz, and determine rcp and c cp using equations (30) and (31): ? = ? ? = = ? ? ? k v v r c l f r o pwmrmp fb e e c cp 49 . 2 10 *1* 130 015 .0 30.1 8.0* 324 *)10 * 10 * 560 (*)7/ 10 * 220 (* ) 10 * 40 * 2( * * * * ) * 2( 3 6 9 23 2 nf r c l c cp e e cp 53 10 * 49.2 )10 * 10 * 560 (*)7/ 10 * 220 ( * 10 * * 10 3 6 9 = = = ? ? , choose c cp =56nf ? = = = 162 324 * 2 1 * 2 1 1 fb fb r r choose r fb1 =162 nf r f c fb c fb 3.12 162 * 10 * 40 * 4 1 * * 4 1 3 1 = = = choose c fb =10nf choose c cp1 =100pf to reduce high frequency noise. downloaded from: http:///
ir3084u page 42 of 47 june 1, 2009 current share loop compensation the crossover frequency of the current share loop ( f ci ) should be at least one decade lower than that of t he voltage loop f c . choose the crossover frequency of current share l oop f ci =4khz , and calculate fmi and c scomp using equations (34) and (35); 0105 .0 )30.1 12(*)30.1 8.0 12( 8.0* 10 * 400 * 10 * 220 * 10 *8.15 ) (*) ( * * * 3 12 3 = ? ? ? = ? ? ? = ? dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f 6 _ 10 * 05.1* * 2* *)] (* * * 2 1[* * * * * * 65.0 ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c + = 6 3 3 3 6 3 3 3 10*05.1* 10*4* 2*) 10*0.1* 130 30.1( 0105 .0*] 130 ) 10*0.1* 130 30.1(* 10* 5600 * 10*4* 2 1[*)7 10*47.0(*34* 130 *12* 10*8.15*65.0 ? ? ? ? ? ? + = 9 10 * 859 . 30 0105 .0*] 266 .2[* 36574 = = 28.2nf choose c scomp =22nf with 5% tolerance for best current sharing be tween phases. downloaded from: http:///
ir3084u page 43 of 47 june 1, 2009 layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of t he pcb layout, therefore minimizing the noise coupled to t he ic. dedicate at least one middle layer for a ground pl ane lgnd. connect the ground tab under the control ic to lgn d plane through a via. place the following critical components on the sam e layer as control ic and position them as close as possible to the respective pins, r osc , r ocset , r vdac , c vdac , c vcc , c ss/del and r cc/del . avoid using any via for the connection. place the compensation components on the same laye r as control ic and position them as close as possi ble to eaout, fb and vdrp pins. avoid using any via for the connection. use kelvin connections for the remote voltage sens e signals, vosns+ and vosns-, and avoid crossing over the fast transition nodes, i.e. switching node s, gate drive signals and bootstrap nodes. control bus signals, vdac, rmpout, iin, vbias, and especially eaout, should not cross over the fast transition nodes. c vcc regfb vid7 vosns- rosc vdac vcc to vin r osc c vdac vosns- c drp r fb1 eaout fb vdrp iin to system lgnd plane lgnd rmpout ss/del enable vrrdy ocset vid6 vid5 vid4 vid3 vid2 vbias r vdac r ocset r vcc c ss/del r regset c cp1 r cp c cp r drp r drp1 r fb c fb to voltage remote sense vosns+ vid_sel vid1 vid0 vsetpt regdrv regset r setpt gnd gnd downloaded from: http:///
ir3084u page 44 of 47 june 1, 2009 metal and solder resist the solder resist should be pulled away from the m etal lead lands by a minimum of 0.06mm. the solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all non solder mask defined (nsmd). therefore pulling the s/r 0.06mm will always ensure nsmd pads. the minimum solder resist width is 0.13mm, therefo re it is recommended that the solder resist is completely removed from between the lead lands form ing a single opening for each group of lead lands. at the inside corner of the solder resist where th e lead land groups meet, it is recommended to provide a fillet so a solder resist width of 0.17mm remains. the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist m is-alignment. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. the single via in the land pad should be tented wi th solder resist 0.4mm diameter, or 0.1mm larger than the diameter of the via. no pcb traces should be routed nor vias placed und er any of the 4 corners of the ic package. doing so can cause the ic to rise up from the pcb resulti ng in poor solder joints to the ic leads. downloaded from: http:///
ir3084u page 45 of 47 june 1, 2009 pcb metal and component placement lead land width should be equal to nominal part le ad width. the minimum lead to lead spacing should be 0.2mm to minimize shorting. lead land length should be equal to maximum part l ead length + 0.2 mm outboard extension + 0.05mm inboard extension. the outboard extension e nsures a large and inspectable toe fillet, and the inboard extension will accommodate any part mis alignment and ensure a fillet. center pad land length and width should be equal t o maximum part pad length and width. however, the minimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. copper and 0.23mm for 3 oz. copper) a single 0.30mm diameter via shall be placed in th e center of the pad land and connected to ground to minimize the noise effect on the ic. downloaded from: http:///
ir3084u page 46 of 47 june 1, 2009 stencil design the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimi ze the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are di fficult to maintain repeatable solder release. the stencil lead land apertures should therefore b e shortened in length by 80% and centered on the lead land. the land pad aperture should be striped with 0.25m m wide openings and spaces to deposit approximately 50% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open. the maximum length and width of the land pad stenc il aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decreas e the incidence of shorting the center land to the lead lands when the part is pushed into the sol der paste. downloaded from: http:///
ir3084u page 47 of 47 june 1, 2009 package information 28l mlpq (5 x 5 mm body) ? ja = 30 o c/w, jc = 3 o c/w data and specifications subject to change without n otice. this product has been designed and qualified for th e consumer market. qualification standards can be found on irs web si te. ir world headquarters: 233 kansas st., el segundo, california 90245, usa t el: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact informati on . www.irf.com downloaded from: http:///

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